1. Field of the Invention
Embodiments of the present invention relate to methods for manufacturing a semiconductor device. More particularly, embodiments of the present invention relate to methods for forming metal lines of a semiconductor device.
2. Discussion of the Related Art
With increasing integration and reduction in the size of semiconductor devices, various configurations have emerged that utilize multilayer lines. Accordingly, the ability to accurately form via-holes and metal lines has become increasingly important in the manufacturing process of semiconductor devices.
FIGS. 1A-1D are sectional views illustrating a conventional method for forming the metal lines of a semiconductor device. As shown in FIG. 1A, a first interlayer dielectric layer 20, made of an oxide layer, is formed on a semiconductor substrate 10. Via-holes are perforated in the first interlayer dielectric layer 20 to form tungsten plugs. After the tungsten plugs are formed in the first interlayer dielectric layer 20, an aluminum layer 30 which is used to form metal lines is deposited over the first interlayer dielectric layer 20 by sputtering. In turn, a photoresist pattern 40 which is used in a subsequent process to form the metal lines is formed over the aluminum layer 30.
As shown in FIG. 1B, the aluminum layer 30 is etched using the photoresist pattern 40 as an etching mask, so as to expose the first interlayer dielectric layer 20, which is for example, made of a SiO2 layer. In the etching of the aluminum layer 30, an etching gas wherein Cl2 and BCl3 are mixed in a predetermined ratio is used.
As shown in FIG. 1C, the residual photoresist pattern 40, which remains after the etching of the aluminum layer 30, is removed via an O2 plasma treatment. Thereafter, a second interlayer oxide layer 50, made of an oxide layer such as, for example, a SiO2 layer, is formed on the aluminum layer 30.
As shown in FIG. 1D, the second interlayer dielectric layer 50 is subjected to subsequent processes (not shown), such as formation of via-holes, formation of tungsten plugs, a Chemical-Mechanical-Polishing (CMP) process, formation of upper metal lines and formation of a passivation layer. Thereafter, the second interlayer dielectric layer 50 is subjected to sintering at 400° C.
Aluminum has a melting point of 660° C. and exhibits poor heat resistance. More particularly, when the aluminum layer 30 is exposed to temperatures above 400° C. while in contact with an oxide layer, such as the second interlayer dielectric layer 50, which is made of a material having a large difference in thermal expansion coefficient with aluminum, an excessively high stress is applied to a contact region between the aluminum layer 30 and the second interlayer dielectric layer 50, and aluminum will flow to alleviate the stress.
When the aluminum layer 30 is exposed to heat during a subsequent thermal treatment, the aluminum flows upwardly and laterally, applying pressure on the second interlayer dielectric layer 50. The stress is concentrated on an upper edge 70 of the aluminum layer 30, causing hillocks on the top of the aluminum layer 30 or cracks 60 in the second interlayer dielectric layer 50.
When the cracks 60 occur in the second interlayer dielectric layer 50, metal grains move through the cracks 60, causing shorts and deteriorating the Electro-Migration (EM) reliability of metal lines.
FIG. 2 illustrates cracks caused in a dielectric layer above the metal lines of a semiconductor device, which are measured using a Scanning Electron Microscope (SEM). Referring to FIG. 2, when a line width of metal lines 3 (for example, aluminum lines) is more than 10 μm, stress is concentrated on an upper edge of a sidewall of the metal line and thus, there is a high probability of cracks in a dielectric layer 7 above the metal lines 3.